A CPU implemented in an analog modular synthesizer

A CPU implemented in an analog modular synthesizer

This runs in the VCV Rack eurorack simulator.

I wrote a thread explaining the CPU on twitter
and a thread explaining just the ripple adder.

TODO list: https://github.com/katef/eurorack-cpu/issues/1

Here's the unannotated screenshot and here's a video of the whole thing running

Instruction formats:

00000: no-op (clears bus)
10ooo: output ALU op to bus
010rr: load reg from bus (keeps bus)
110rr: output register to bus
0110n: load ALU operand (clears bus)
0111i: output immediate to bus

ooo = alu op
rr = register number
n = alu operand
i = immediate

Fetch and Decode

and a video of it running

Data bus

3-Stage Clock

A single register

Register bank

and a video of it running

Immediate value

ALU

Ripple carry adder

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Comments
  • TODO

    TODO

    • there's no reason the data bus can't be 16 bit
    • really there's no reason why the data can't be analog, too. i could extend the ALU with operations for opamps
    • more ALU ops, 3 bits isn't enough
    • ram (i'd want denser polyphonic sample & holds for this)
    • unsure if i want to keep the 5-bit opcodes and treat them as microcode, with a wider instruction bus driving them. or replace the fetch stage with wider instructions in the first place
    • midi input for instructions
    • rom for instructions, and a program counter
    • conditional branch
    • I/O to midi. should figure out if i want the data bus to be analog first though
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