The DNN+NeuroSim framework was developed by Prof. Shimeng Yu's group (Georgia Institute of Technology). The model is made publicly available on a non-commercial basis. Copyright of the model is maintained by the developers, and the model is distributed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International Public License
1. Validate with real silicon data. 2. Add synchronous and asynchronous mode. 3. Update technology file for FinFET. 4. Add level shifter for eNVM.
validated = true; // false: no calibration factor // true: validated by silicon data synchronous = true; // false: asynchronous // true: synchronous, clkFreq decided by sensing delay
1. VGG8 on cifar10 8-bit "WAGE" mode pretrained model is uploaded to './log/VGG8.pth' 3. DenseNet40 on cifar10 8-bit "WAGE" mode pretrained model is uploaded to './log/DenseNet40.pth' 5. ResNet18 on imagenet "FP" mode pretrained model is loaded from 'https://download.pytorch.org/models/resnet18-5c106cde.pth'
python inference.py --dataset cifar10 --model VGG8 --mode WAGE python inference.py --dataset cifar10 --model DenseNet40 --mode WAGE python inference.py --dataset imagenet --model ResNet18 --mode FP
For estimation of on-chip training accelerators, please visit released V2.1 DNN+NeuroSim V2.1
In Pytorch/Tensorflow wrapper, users are able to define network structures, precision of synaptic weight and neural activation. With the integrated NeuroSim which takes real traces from wrapper, the framework can support hierarchical organization from device level to circuit level, to chip level and to algorithm level, enabling instruction-accurate evaluation on both accuracy and hardware performance of inference.
This research is supported by NSF CAREER award, NSF/SRC E2CDA program, and ASCENT, one of the SRC/DARPA JUMP centers.
If you use the tool or adapt the tool in your work or publication, you are required to cite the following reference:
X. Peng, S. Huang, Y. Luo, X. Sun and S. Yu, ※DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies, § IEEE International Electron Devices Meeting (IEDM), 2019.
If you have logistic questions or comments on the model, please contact
Documents/DNN NeuroSim V1.3 Manual.pdf
- DNN_NeuroSim wrapped by Pytorch: 'Inference_pytorch'
- NeuroSim under Pytorch Inference: 'Inference_pytorch/NeuroSIM'
Installation steps (Linux)
- Get the tool from GitHub
git clone https://github.com/neurosim/DNN_NeuroSim_V1.3.git
Train the network to get the model for inference (can be skipped by using pretrained default models)
Compile the NeuroSim codes
- Run Pytorch/Tensorflow wrapper (integrated with NeuroSim)
For the usage of this tool, please refer to the manual.
References related to this tool
- X. Peng, S. Huang, Y. Luo, X. Sun and S. Yu, ※DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies, § IEEE International Electron Devices Meeting (IEDM), 2019.
- X. Peng, R. Liu, S. Yu, ※Optimizing weight mapping and data flow for convolutional neural networks on RRAM based processing-in-memory architecture, § IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
- P.-Y. Chen, S. Yu, ※Technological benchmark of analog synaptic devices for neuro-inspired architectures, § IEEE Design & Test, 2019.
- P.-Y. Chen, X. Peng, S. Yu, ※NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning, § IEEE Trans. CAD, 2018.
- X. Sun, S. Yin, X. Peng, R. Liu, J.-S. Seo, S. Yu, ※XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks,§ ACM/IEEE Design, Automation & Test in Europe Conference (DATE), 2018.
- P.-Y. Chen, X. Peng, S. Yu, ※NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures, § IEEE International Electron Devices Meeting (IEDM), 2017.
- P.-Y. Chen, S. Yu, ※Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing,§ IEEE International Symposium on Circuits and Systems (ISCAS), 2016.
- P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, ※Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,§ IEEE Design, Automation & Test in Europe (DATE), 2015.
- S. Wu, et al., ※Training and inference with integers in deep neural networks,§ arXiv: 1802.04680, 2018.